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DFT MBIST Staff Engineer
Job Description
Position Summary
We are seeking a highly experienced DFT MBIST Staff Engineer to join our SoC Design-for-Test (DFT) team as a contractor. This role focuses on hands-on Memory Built-In Self-Test (MBIST) implementation using Synopsys MBIST (SMS).
The ideal candidate will be an independent contributor capable of owning the complete MBIST lifecycle, from insertion and top-level integration through verification, simulation, pattern generation, diagnostics, and silicon bring-up, with minimal supervision.
Key Responsibilities
Perform MBIST insertion for complex SoC designs using Synopsys SMS.
Integrate and verify MBIST functionality at the SoC top level.
Develop, execute, and debug MBIST simulations using Synopsys VCS, including:
RTL simulations
No-delay gate-level simulations
With-delay, timing-aware simulations
Generate and validate MBIST test patterns using VecGen.
Debug RTL, simulation, and MBIST integration issues.
Support silicon bring-up, characterization, and post-silicon debugging related to MBIST, memory failures, and DFT infrastructure.
Collaborate with DFT, RTL, Physical Design, and Product Engineering teams to resolve implementation issues.
Independently drive issue resolution and document implementation flows, debug procedures, and findings.
Requirements
Required Qualifications
8+ years of hands-on DFT experience, with significant expertise in MBIST.
Strong experience with Synopsys MBIST (SMS), preferably SMS5 and/or SMS6.
Proficiency in Synopsys VCS for MBIST verification and simulation.
In-depth understanding of the complete MBIST flow, including:
MBIST insertion and top-level integration
Verification, simulation, and debugging
Pattern generation using VecGen
MBIST diagnostics
Strong knowledge of MBIST test algorithms, including March algorithms.
Experience with memory repair schemes, including BIRA/BISR, redundancy analysis, and spare row/column allocation.
Hands-on experience running and debugging no-delay and with-delay simulations.
Experience supporting silicon bring-up, post-silicon debug, and root-cause analysis of MBIST and memory-related failures.
Strong debugging skills across RTL, MBIST, and simulation environments.
Experience with large, complex SoC designs containing multiple memory instances.
Familiarity with Verilog/SystemVerilog and standard DFT methodologies.
Ability to work independently with minimal supervision.
Preferred Qualifications
Experience with advanced SoC DFT integration.
Familiarity with ATPG and scan insertion flows.
Scripting experience with Tcl, Perl, or Python to automate MBIST workflows and debugging.
Experience working in fast-paced semiconductor product development environments.
Key Technical Skills
Synopsys MBIST — SMS5/SMS6
Synopsys VCS
MBIST Insertion and Top-Level Integration
MBIST Verification and Diagnostics
VecGen Pattern Generation
MBIST Repair Schemes and Memory Test Algorithms
No-Delay and With-Delay Simulation and Debugging
Silicon Bring-Up and Post-Silicon Debug
SoC DFT Integration
Verilog/SystemVerilog
Tcl, Perl, and Python Scripting
Strong Communication and Independent Problem-Solving Skills
Ideal Candidate Profile
The ideal contractor is a senior, hands-on MBIST engineer who can become productive quickly with minimal ramp-up. The candidate should have deep expertise in Synopsys SMS and VCS, excellent debugging and root-cause analysis skills, and a proven track record of independently delivering MBIST implementation, verification, and debugging for complex SoC designs.
Interested candidates: Please share your updated resume along with your total DFT/MBIST experience, Synopsys SMS version experience (SMS5/SMS6), VCS and VecGen expertise, current location, work authorization, and preferred engagement type (C2C or W2).