Lead ASIC DFT Staff Engineer

Experience: 10+ years of hands-on ASIC Design-for-Test (DFT) experience

Key Technical Skills

• Scan Architecture, Scan Insertion, and Scan Chain Stitching
• ATPG (Automatic Test Pattern Generation)
• MBIST/LBIST Implementation and Verification
• Timing Simulations and SDF (Standard Delay Format)
• SDC (Synopsys Design Constraints)
• PSV, Diagnosis, and Silicon Debug
• Pattern Retargeting and Pattern Porting
• DRC (Design Rule Check) Analysis
• Synopsys TetraMAX, DFTMAX, and related DFT tools

Role Summary

We are seeking a highly experienced Lead ASIC DFT Staff Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs.

This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation. The engineer will lead cross-functional debugging efforts and drive resolution of critical silicon issues.

The ideal candidate will have extensive hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debugging, along with the ability to evaluate and adopt emerging DFT methodologies to improve design robustness, product quality, and manufacturing yield.

Key Responsibilities

• Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
• Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high fault coverage and robust testability.
• Own MBIST/LBIST integration, implementation, verification, and debugging throughout design and silicon bring-up phases.
• Perform DFT debugging, failure analysis, root-cause investigation, and fault-coverage closure for complex silicon issues.
• Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
• Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
• Support ATPG pattern generation, ATPG simulations, DRC analysis, test-coverage analysis, diagnosis, and debugging.
• Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
• Review RTL, synthesis, logical equivalence checking (LEC), and physical design impacts on DFT implementation and test quality.
• Serve as a technical escalation point for advanced DFT and post-silicon debugging issues.
• Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
• Develop scripts and automation using Tcl, Perl, or Python to improve workflow efficiency and debugging productivity.

Required Skills & Qualifications

• Strong hands-on ASIC DFT experience with end-to-end implementation ownership.
• Solid understanding of DFT fundamentals, fault models, test techniques, and test-coverage concepts.
• Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debugging.
• Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
• Proven experience in scan insertion, ATPG setup, simulation, debugging, and DRC analysis.
• Experience with MBIST implementation and verification; Synopsys SMS experience preferred.
• Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
• Strong understanding of PLLs, RTL design, synthesis flows, LEC, and physical design implementation.
• Proven experience in post-silicon debugging and silicon bring-up.
• Experience with large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
• Excellent communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

• MBIST post-silicon validation.
• ATPG simulations and fault-coverage debugging.
• DFT RTL, DFD (Design-for-Debug), DFT verification, and IP-level DFT integration.
• DFT SDC creation and DFT timing-closure support.
• Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
• Tcl/Perl scripting for DFT automation, reporting, and debugging.
• Experience across multiple ASIC technology nodes and complex product development cycles.
• Familiarity with yield learning, silicon diagnosis, and manufacturing test optimization.

Ideal Candidate Profile

The ideal candidate is a senior-level DFT technical leader with strong hands-on implementation expertise and end-to-end ownership of complex ASIC/SoC test solutions. The candidate should be capable of leading DFT architecture and sign-off, resolving advanced silicon issues, improving test coverage, and mentoring engineering teams while working independently in a remote environment.

Interested candidates: Please share your updated resume along with your total ASIC DFT experience, scan/ATPG/MBIST expertise, EDA tool experience, post-silicon debug experience, work authorization, and preferred engagement type (C2C or W2).